The embodiments of the invention generally relate to Cadence parameterized cells that allow programmatic control over schematic and layout attributes in a very large scale integration (VLSI) circuit design.
One process known as Cadence parameterized cells (“p-cells”) is a useful technique for generating circuit designs based on a set of inputs. Logic cells in the p-cells design methodology are essentially routines that are called by the programs that create or modify layouts. The parameters that define a cell in such a library include gate widths, number of fingers, etc. A typical use of such p-cells is to couple the schematic and physical views of a cell, so that the routines that create cells in the schematic for a circuit also create the drawing shapes that correspond to the parameter settings for each instance of a cell.
In addition, the OpenAccess data format has adopted the concept of parameterized cells and includes a parameterized via cell as part of its definition. By parameterizing different characteristics of the logic cells, an effectively infinite number of combinations of cells is possible for a given placement. In this way, automated tools can then optimize across this set of combinations to reduce power or increase frequency, with very low overhead in supporting the shared circuit library when compared to the otherwise near-infinite variety of cell personalizations that might be needed in a full-custom design.
The recent introduction of via cells having many non-schematic parameters that correlate with physical manufacturing sensitivity has presented a new capability: optimizing p-cells at the shapes level for the purpose of yield improvement. There is currently no automated solution available for optimizing yield in this way.
In some cases of integrated circuit design representation and automation, there is a one-to-one correspondence between schematic parameters and layout parameters (e.g., device dimensions). In other cases—such as via overlaps—there is no aspect of the schematic that represents a particular geometric configuration of layout shapes.
This disclosure presents a method of layout optimization containing parameterized cells that includes reading a physical design containing parameterized cells and creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters. Such constraints can comprise balanced overlaps for OpenAccess vias.
These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.